This invention relates to the formation of liner films for dual damascene metal chip-level interconnects.
In a conventional dual damascene metal process, thin liners, such as refractory liners, are sputtered into a recessed feature, which is then coated with a thicker and more conductive film, such as copper, that can carry current during device operation.
In the case of Cu interconnects with a SiO2 dielectric, for example, a first metal liner film, such as Ta or Ti, may be applied to provide adhesion, low contact resistance, and reduced contamination of the surrounding dielectric by the subsequently deposited overlying interconnect film or structure. A second metal nitride liner film such as TaN, TiN or WNxmay be applied thereon to improve the barrier performance. The next film, such as a Cu seed, is applied to facilitate the interconnect structure formation, for example electroplated Cu fill. Finally, the wafer is transferred to another apparatus that accomplishes the interconnect structure formation.
For the case of Cu interconnects with a fluorinated dielectric, the Ta or Ti deposition step is omitted, and the metal nitride is deposited directly onto the dielectric, since a pure metal, such as Ta or Ti, can react with fluorine to form compounds that render the interface between the dielectric and liner film weak against film delamination. This would be equally true for other mobile reactive species that may be present in a dielectric.
Liner films are commonly deposited by conventional physical vapor deposition (PVD), which results in a poor coverage ratio for the recessed surface fcaturcs, such as contacts, trenches and vias, versus the upper surfaces of the wafer. This is particularly true for high aspect ratio features. Ionized PVD and chemical vapor deposition (CVD) have been developed, which provide films having different characteristics than those resulting from conventional PVD. In particular, ionized PVD greatly enhances coverage of the feature bottom and enhances sidewall coverage. In general, as is well known in the art, ionized PVD involves sputtering particles from a source and converting the particles to positive ions by a high density plasma and applying an electric field, or bias, to direct the ions into the recessed features through a potential difference. There are numerous apparatuses available to one skilled in the art for performing ionized PVD, one example of which is discussed in copending application Ser. No. 09/442,600, now U.S. Pat. No. 6,287,435, entitled xe2x80x9cMethod and Apparatus for Ionized Physical Vapor Deposition,xe2x80x9d and incorporated by reference herein.
CVD can also be used to deposit films. Such films cover features differently than do PVD films. CVD processes use reactive precursors, which may contain a halogen, such as fluorine or chlorine. The precursors diffuse to the substrate surface where they react and leave a metal-containing film behind. The reaction can occur through either thermal or plasma-enhanced mechanisms. Thermal CVD can provide uniform coverage of an entire feature. In general, as is well known in the art, thermal CVD is a high temperature process in which the reactive precursors are passed over a heated substrate, and they readily decompose in the high temperature environment of the reactor and recombine to form a conformal metal-containing film on the heated substrate. Plasma enhanced CVD provides coverage similar to that provided by ionized PVD though with less overhang near the feature opening. Plasma enhanced CVD introduces a plasma to produce reactive chemical species from the reactive precursors, which combine to deposit the desired film on the surface of the substrate. The energetic enhancement provided by plasma enhanced CVD allows layers to be deposited at a significantly lower temperature than those deposited by unassisted thermal CVD methods. There are numerous apparatuses available to one skilled in the art for performing thermal and/or plasma enhanced CVD, one example of which is discussed in copending application Ser. No. 09/300,632 entitled xe2x80x9cCVD of Integrated Ta and TaNx Films from Tantalum Halide Precursors,xe2x80x9d now U.S Pat. No. 6,410,432 issued Jun. 25, 2002, incorporated by reference herein.
Typically, electrically conductive refractory metal nitrides such as Ta2N, TaSiN, TiN, WNx and WSiN can be employed as a diffusion barrier to prevent migration of foreign particles into the dielectric or the semiconductor substrate beneath the wiring. At typical process temperatures up to about 450xc2x0 C., such films are moderately conductive, are stable against thermal degradation and chemical reactions, and effectively block the unwanted migration of atoms if the film thickness is sufficient at all points along the feature. However, diffusion barrier film thickness should be minimized everywhere to allow more room for conductive copper fill or other conductive metal fill and easy removal from the upper surface by chemical mechanical polishing (CMP), but particularly at the feature bottom to achieve desirable low contact resistance for the device. In practice, the product of the film resistivity and thickness must be engineered to allow device contact resistance specifications of, for example, about 2-4 Ohms per contact for a 0.1 xcexcm IC product node. Thus, a balance must be struck between having enough diffusion barrier material to block the passage of diffusing atoms from the metal layer, the dielectric and the interconnect metal, and having a thin enough layer to permit good electrical contact and cost-effective manufacturing.
The problem of high contact resistance is more severe for more highly resistive metal nitrides including amorphous ternary compounds such as TaSiN and WSiN, amorphous TaN, and for insulating diffusion barriers such as Si3N4, all of which provide exceptionally robust diffusion barrier properties.
With all of the various methods in existence for forming various layers on a wafer, a need exists to establish an effective method for forming the liners for dual damascene wiring.
The present invention provides a diffusion barrier stack integral with a dielectric for use in an interconnect structure, the dielectric topography having surface features, such as contacts, trenches and vias, and a method for forming the diffusion barrier stacks on the dielectric, the method including depositing alternating layers of a metal and an electrically resistive diffusion barrier, such as a metal nitride or an insulating silicon nitride. Each layer has a thickness sufficient to perform a desired function in the structure. The internal metal layers have a thickness sufficient to function as contact facilitation layers. The electrically resistive diffusion barrier layers have individual layer thicknesses sufficient to allow passage of current through the layer and a total thickness of all diffusion barrier layers sufficient to block passage of diffusing atoms. The terminal layer of the stack functions as an interconnect metal stabilization layer.